STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
DS3 System Side Interface
RGAPCLK/RSCLK Output Y3
Framer Recovered Gapped Clock (RGAPCLK).
RGAPCLK is valid when the TEMAP is configured as a
DS3 framer by setting the OPMODE[1:0] bits in the
Global Configuration register and the RXGAPEN bit in
the DS3 Master Unchannelized Interface Options
register.
RGAPCLK is the recovered clock and timing reference
for RDATO. RGAPCLK is held either high or low
during bit positions which correspond to overhead.
Framer Recovered Clock (RSCLK). RSCLK is valid
when the TEMAP is configured as a DS3 framer by
setting the OPMODE[1:0] bits in the Global
Configuration register.
RSCLK is the recovered clock and timing reference for
RDATO, RFPO/RMFPO, and ROVRHD.
This signal shares a signal pin with ICLK[1]. When
enabled for unchannelized DS3 operation this signal
will be RGAPCLK/RSCLK, otherwise it will be ICLK[1].
RDATO
Output AA5
Framer Receive Data (RDATO). RDATO is valid when
the TEMAP is configured as a DS3 framer by setting
the OPMODE[1:0] bits in the Global Configuration
register. RDATO is the received data aligned to
RFPO/RMFPO and ROVRHD.
RDATO is updated on either the falling or rising edge
of RGAPCLK or RSCLK, depending on the value of
the RSCLKR bit in the DS3 Master Unchannelized
Interface Options register. By default RDATO will be
updated on the falling edge of RGAPCLK or RSCLK.
This signal shares a signal pin with ID[1] and MVID[1].
This signal will be RDATO only when enabled for
unchannelized DS3 operation.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
29
PMC [ PMC-SIERRA, INC ]
