STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Serial PCM interfaces to each T1 framer allow 1.544 Mbit/s ingress/egress
system interfaces to be directly supported.
A Scaleable Bandwidth Interconnect (SBI) high density byte serial system
interface provides higher levels of integration and dense interconnect. The SBI
bus interconnects up to 84 T1s or 63 E1. The SBI allows transmit timing to be
mastered by either the TEMAP or link layer device connected to the SBI bus.
This interconnect allows up to 3 TEMAPs to be connected in parallel to provide
the full complement of 84 T1s or 63 E1s of traffic. In addition to clear channel
T1s and E1s the TEMAP can transport framed or unframed DS3 links over the
SBI bus.
When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TEMAP
accepts and outputs either or both digital B3ZS-encoded bipolar and unipolar
signals compatible with M23 and C-bit parity applications.
In the DS3 receive direction, the TEMAP frames to DS3 signals with a maximum
-3
average reframe time of 1.5 ms in the presence of 10 bit error rate and detects
line code violations, loss of signal, framing bit errors, parity errors, C-bit parity
errors, far end block errors, AIS, far end receive failure and idle code. The DS3
framer is an off-line framer, indicating both out of frame (OOF) and change of
frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) are still
indicated while the framer is OOF, based on the previous frame alignment. When
in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and
Control (FEAC) channels are extracted. HDLC receivers are provided for Path
Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC
channels are detected and are available through the microprocessor port.
Error event accumulation is also provided by the TEMAP. Framing bit errors, line
code violations, excessive zeros occurrences, parity errors, C-bit parity errors,
and far end block errors are accumulated. Error accumulation continues even
while the off-line framers are indicating OOF. The counters are intended to be
-3
polled once per second, and are sized so as not to saturate at a 10 bit error
rate. Transfer of count values to holding registers is initiated through the
microprocessor interface.
In the DS3 transmit direction, the TEMAP inserts DS3 framing, X and P bits.
When enabled for C-bit parity operation, bit-oriented code transmitters and
HDLC transmitters are provided for insertion of the FEAC channels and the Path
Maintenance Data Links into the appropriate overhead bits. Alarm Indication
Signals, Far End Receive Failure and idle signal can be inserted using either
internal registers or can be configured for automatic insertion upon received
errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of
the first M sub-frame) is forced to toggle so that downstream equipment will not
confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
22
PMC [ PMC-SIERRA, INC ]
