STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Table 44: Egress Interface Input Timing - Clock Master : Clear Channel
Mode (Figure 66)
Symbol
Description
Min
Max
Units
7,9
tSECLK
tHECLK
30
30
ns
ns
ECLK[x] to ED[x] Set-up Time
8,9
ECLK[x] to ED[x] Hold Time
Figure 66: Egress Interface Input Timing - Clock Master : Clear Channel
Mode
Valid
tSECLK
ED[x]
tHECLK
ECLK[x]
Note: ECLK[x] is an output derived from CTCLK.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
223