STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
13.6 SBI DROP Bus Interface Timing
Figure 51: SBI DROP Bus T1/E1 Functional Timing
SSS
SC1FP
SSS
SDDATA[7:0]
SDPL
C1
V3
V3
V3 byte#4. V5 byte#9.
SSS
SSS
SSS
SSS
SSS
SDV5
SDDP
SBIACT
Figure 51 illustrates the operation of the SBI DROP Bus, using a negative
justification on the second to last V3 octet as an example. The justification is
indicated by asserting SDPL high during the V3 octet. The timing diagram also
shows the location of one of the tributaries by asserting SDV5 high during the V5
octet. The SBIACT signal is shown for the case in which TEMAP is driving
SPE#1 onto the SBI DROP bus.
Figure 52: SBI DROP Bus DS3 Functional Timing
SSS
SC1FP
SSS
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
SDDATA[7:0
SDPL
C1
H3
H3
H3
SSS
SSS
SSS
SSS
SSS
SDV5
SDDP
SBIACT
Figure 52 shows three DS-3 tributaries mapped onto the SBI bus. A negative
justification is shown for DS-3 #2 during the H3 octet with SDPL asserted high. A
positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3
which has SDPL asserted low. The SBIACT signal is shown for the case in
which TEMAP is driving SPE#2 (DS-3#2) onto the SBI DROP bus.
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PMC [ PMC-SIERRA, INC ]
