STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
The Egress Interface is configured for the Clock Master: Clear Channel mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is sampled on the rising edge of the ECLK[x] output. When the the EDE bit
in the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is
sampled on the falling edge of ECLK[x], and the functional timing is described by
Figure 54 with the ECLK[x] signal inverted.
Figure 55: T1 and E1 Egress Interface Clock Slave: Clear Channel Mode
ECLK[x]
ED[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
The Egress Interface is configured for the Clock Slave: Clear Channel mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is clocked in on the rising edge of the ECLK[x] input. When the EDE bit in
the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is
sampled on the falling edge of ECLK[x], and the functional timing is described by
Figure 55 with the ECLK[x] signal inverted.
13.9 Ingress Serial Clock and Data Interface Timing
Figure 56: T1 and E1 Ingress Interface Clock Master: Clear Channel Mode
I CLK[x]
I D[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
The Ingress Interface is configured for the Clock Slave: Clear Channel mode by
writing to IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register.
ID[x] is updated on the falling edge of the ICLK[x] input. When the IDE bit in the
T1/E1 Serial Interface Configuration register is set to logic 1, then ID[x] is
updated on the rising edge of ICLK[x], and the functional timing is described by
Figure 56 with the ICLK[x] signal inverted.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
200
PMC [ PMC-SIERRA, INC ]
