STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
13.7 SBI ADD Bus Interface Timing
The SBI ADD bus functional timing for the transfer of tributaries whether T1/E1 or
DS3 is the same as for the SBI DROP bus. The only difference is that the SBI
ADD bus has one additional signal: the SAJUST_REQ output. The
SAJUST_REQ signal is used to by the TEMAP in SBI master timing mode to
provide transmit timing to SBI link layer devices.
Figure 53: SBI ADD Bus Justification Request Functional Timing
SSS
SREFCLK
SSS
SC1FP
SSS
SADATA[7:0]
SAPL
DS-3 #1 DS-3 #2DS-3 #3DS-3 #1
C1
H3
H3
H3
SSS
SSS
SSS
SSS
SAV5
SADP
SAJUST_REQ
Figure 53 illustrates the operation of the SBI ADD Bus, using positive and
negative justification requests as an example. (The responses to the justification
requests would take effect during the next multi-frame.) The negative
justification request occurs on the DS-3#3 tributary when SAJUST_REQ is
asserted high during the H3 octet. The positive justification occurs on the DS-3#2
tributary when SAJUST_REQ is asserted high during the first DS-3#2 octet after
the H3 octet.
13.8 Egress Serial Clock and Data Interface Timing
By convention in the following functional timing diagrams, the first bit transmitted
in each channel shall be designated bit 1 and the last shall be designated bit 8.
Each of the Ingress and Egress Master and Clock Modes apply to both T1 and
E1 configurations with the exception of the 2.048MHz T1 Clock Slave Modes.
Figure 54: T1 and E1 Egress Interface Clock Master: Clear Channel Mode
ECLK[x]
ED[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
199
PMC [ PMC-SIERRA, INC ]
