STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Figure 43: Framer Mode DS3 Receive Output Stream
RSCLK
INFO INFO INFO
INFO INFO INFO
INFO INFO
INFO
INFO INFO
RDATO
F
X
X
INFO INFO INFO
RFPO/RMFPO
ROVRHD
Figure 44: Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK
INFO INFO
INFO
INFO INFO INFO
INFO INFO
INFO
INFO INFO
RDATO
INFO INFO INFO
The DS3 Framer Only Mode Receive Output Stream diagram (Figure 43) shows
the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the
OPMODE[1:0] bits are set to “DS3 Framer Only mode” in the Global
Configuration register. Figure 43 shows the data streams when the TEMAP is
configured for the DS3 receive format. If the RXMFPO bit in the DS3 Master
Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse
high for one RSCLK cycle on first bit of each M-subframe with alignment to the
RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown Figure
43), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output
stream. ROVRHD will be high for every overhead bit position on the RDATO
data stream. Figure 44 shows the output data stream with RGAPCLK in place of
RSCLK when the RXGAPEN bit in the DS3 Master Unchannelized Interface
Options register set to logic 1. RGAPCLK remains high during the overhead bit
positions.
13.3 Telecom DROP Bus Interface Timing
Figure 45 shows the function of the various telecom DROP bus signals in AU3
mode. Data on LDDATA[7:0] is sampled on the rising edge of LREFCLK. The
bytes forming the three STS-1 synchronous payload envelopes are identified
when the LDPL signal is high. In this diagram, a negative stuff event is shown
occurring on STS-1 #2 and a positive stuff event on STS-1 #3. The LDC1J1V1
signal pulses high, while LDPL is set low, to mark the C1 byte of the first STS-1
in every frame of the STS-3 transport envelope. The LDC1J1V1 signal is high
when the LDPL signal is high to mark every J1 byte of each of the three STS-1
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