STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
13.2 DS3 System Side Interface Timing
Figure 41: Framer Mode DS3 Transmit Input Stream
TICLK or RCLK
INFO 82 INFO 83 INFO 84
INFO 82 INFO 83 INFO 84
TDATI
X2
INFO 82 INFO 83 INFO 84
INFO 1 INFO 2
INFO 1 INFO 2 INFO 3
X1
F4
TFPI/TMFPI
TFPO/TMFPO
Figure 42: Framer Mode DS3 Transmit Input Stream With TGAPCLK
TGAPCLK
TDATI
INFO 1
INFO 2 INFO 3
INFO 4
INFO 83 INFO 84
INFO 1
INFO 83 INFO 84
INFO 1
INFO 2 INFO 3
INFO 81 INFO 82 INFO 83
The Framer Mode DS3 Transmit Input Stream diagram (Figure 41) shows the
expected format of the inputs TDATI and TFPI/TMFPI along with TICLK and the
output TFPO/TMFPO when the OPMODE[1:0] bits are set to “DS3 Framer Only
mode” in the Global Configuration register. If the TXMFPI bit in the DS3 Master
Unchannelized Interface Options register is logic 0, then TFPI is valid, and the
TEMAP will expect TFPI to pulse for every DS3 overhead bit with alignment to
TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the TEMAP
will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If
the TXMFPO bit in the DS3 Master Unchannelized Interface Options register is
logic 0, then TFPO is valid, and the TEMAP will pulse TFPO once every 85
TICLK cycles, providing upstream equipment with a reference DS3 overhead
pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the TEMAP
will pulse TMFPO once every 4760 TICLK cycles, providing upstream equipment
with a reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary.
There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. When the
DS3 interface is loop timed by setting the LOOPT bit in the DS3 Master Data
Source register, RCLK replaces TICLK as the transmit timing reference and all
timing is relative to RCLK.
The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN
bit in the DS3 Master Unchannelized Interface Options register is set to logic 1,
as in Figure 42. TGAPCLK remains high during the overhead bit positions.
TDATI is sampled on the active edge of TGAPCLK when TXGAPEN is set to
logic 1 and on the active edge of TICLK when TXGAPEN is set to logic 0. The
TDATIFALL bit in the DS3 Master Unchannelized Interface Options register
selects the active edge of TICLK or TGAPCLK for sampling TDATI.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
190
PMC [ PMC-SIERRA, INC ]
