STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
13
FUNCTIONAL TIMING
13.1 DS3 Line Side Interface Timing
All functional timing diagrams assume that polarity control is not being applied to
input and output data and clock lines (i.e. polarity control bits in the TEMAP
registers are set to their default states).
Figure 37: Receive Bipolar DS3 Stream
RCLK
LCV
RPOS
3 consec 0s
RNEG
The Receive Bipolar DS3 Stream diagram (Figure 37) shows the operation of the
TEMAP while processing a B3ZS encoded DS3 stream on inputs RPOS and
RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated
corresponds to a valid B3ZS signature. A line code violation is declared upon
detection of three consecutive zeros in the incoming stream, or upon detection of
a bipolar violation which is not part of a valid B3ZS signature.
Figure 38: Receive Unipolar DS3 Stream
RCLK
X1 BIT INFO 1
INFO 84
INFO 84
C BIT
INFO 1 INFO 2
OR F BIT
INFO 3
INFO 4 INFO 5
X2 BIT
RDAT
RLCV
LCV INDICATION
OR P OR M BIT
The Receive Unipolar DS3 Stream diagram (Figure 38) shows the complete DS3
receive signal on the RDAT input. Line code violation indications, detected by an
upstream B3ZS decoder, are indicated on input RLCV. RLCV is sampled each
bit period. The PMON Line Code Violation Event Counter is incremented each
time a logic 1 is sampled on RLCV.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
188
PMC [ PMC-SIERRA, INC ]
