STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
The pattern generator consists of a 32 bit shift register and a single XOR gate.
The XOR gate output is fed into the first stage of the shift register. The XOR
gate inputs are determined by values written to the length register (PL[4:0]) and
the tap register (PT[4:0], when the PS bit is low). When PS is high, the pattern
detector functions as a recirculating shift register, with length determined by
PL[4:0].
Generating and detecting repetitive patterns
When a repetitive pattern (such as 1-in-8) is to be generated or detected, the PS
bit must be set to logic 1. The pattern length register must be set to (N-1), where
N is the length of the desired repetitive pattern. Several examples of
programming for common repetitive sequences are given below in the Common
Test Patterns section.
For pattern generation, the desired pattern must be written into the PRGD
Pattern Insertion registers. The repetitive pattern will then be continuously
generated. The generated pattern will be inserted in the output data stream, but
the phase of the pattern cannot be guaranteed.
For pattern detection, the PRGD will determine if a repetitive pattern of the length
specified in the pattern length register exists in the input stream. It does so by
loading the first N bits from the data stream, and then monitoring to see if the
pattern loaded repeats itself error free for the subsequent 48 bit periods. It will
repeat this process until it finds a repetitive pattern of length N, at which point it
begins counting errors (and possibly re-synchronizing) in the same way as for
pseudo-random sequences. Note that the PRGD does NOT look for the pattern
loaded into the Pattern Insertion registers, but rather automatically detects any
repetitive pattern of the specified length. The precise pattern detected can be
determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD
Control register, and reading the Pattern Detector registers (which will then
contain the 32 bits detected immediately prior to the strobe).
Common Test Patterns
The PRGD can be configured to monitor the standardized pseudo random and
repetitive patterns described in ITU-T O.151. The register configurations
required to generate these patterns and others are indicated in Table 30 and
Table 31 below:
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