STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
2
3
4
5
6
7
8
9
Unused
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
Unused
Unused
Unused
Unused
Unused
Unused
Unused
12.8 Serial Clock and Data Format
The Serial Clock and Data interfaces are able to carry the complete payload for
28 T1s or 21 E1s. Each T1 or E1 is assigned to two transmit pins and two
receive data pins for the payload and clock.
In T1 mode, all 28 pairs of clock and data pins are used in each direction.
In normal E1 mode, the first 21 pairs of clock and data pins are used in each
direction. The clock and data pins numbered between 22 and 28 are not
defined, as the 22nd through 28th PMON blocks are not used in this mode.
In ITU-T G.747 mutiplexed E1 mode, every fourth set of clock and data pins are
not used in each direction. (i.e. Pins 1-3, 5-7, 9-11, 13-15, 17-19, 21-23, 25-27
are defined while pins 4, 8, 12, 16, 20, 24, and 28 are not defined.) This is
because the 4th, 8th, 12th, 16th, 20th, 24th and 28th PMON blocks are not used in
this mode.
12.9 PRGD Pattern Generation
The pattern generator can be configured to generate pseudo random patterns or
repetitive patterns as shown in Figure 30 below:
Figure 30: PRGD Pattern Generator
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
176
PMC [ PMC-SIERRA, INC ]
