STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
On the DROP BUS the TEMAP is timing master as determined by the arrival rate
of data over the SBI.
On the ADD BUS the TEMAP can be either the timing master or the timing slave.
When the TEMAP is the timing slave it receives its transmit timing information
from the arrival rate of data across the SBI ADD bus. When the TEMAP is the
timing master it signals devices on the SBI ADD bus to speed up or slow down
with the justification request signal, SAJUST_REQ. The TEMAP as timing master
indicates a speedup request to a Link Layer SBI device by asserting the
justification request signal high during the V3 or H3 octet. When this is detected
by the Link Layer it will speed up the channel by inserting extra data in the next
V3 or H3 octet. The TEMAP indicates a slowdown request to the Link Layer by
asserting the justification request signal high during the octet after the V3 or H3
octet. When detected by the Link Layer it will retard the channel by leaving the
octet following the next V3 or H3 octet unused. Both advance and retard rate
adjustments take place in the frame or multi-frame following the justification
request.
SBI Link Rate Information
The TEMAP SBI bus provides a method for carrying link rate information
between devices. This is optional on a per channel basis. Two methods are
specified, one for T1 and E1 channels and the second for DS3 channels. Link
rate information is not available for TVTs. These methods use the reference
19.44MHz SBI clock and the SC1FP frame synchronization signal to measure
channel clock ticks and clock phase for transport across the bus.
The T1 and E1 method allows for a count of the number of T1 or E1 rising clock
edges between 2 KHz SC1FP frame pulses. This count is encoded in
ClkRate[1:0] to indicate that the nominal number of clocks, one more than
nominal or one less than nominal should be generated during the SC1FP period.
This method also counts the number of 19.44MHz clock rising edges after
sampling SC1FP high to the next rising edge of the T1 or E1 clock, giving the
ability to control the phase of the generated clock. The link rate information
passed across the SBI bus via the V4 octet and is shown in Table 19.
Table 20 shows the encoding of the clock count, ClkRate[1:0], passed in the link
rate octet.
Table 19: SBI T1/E1 Link Rate Information
SC1FP
S S S
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165
PMC [ PMC-SIERRA, INC ]
