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PM5365-PI 参数 Datasheet PDF下载

PM5365-PI图片预览
型号: PM5365-PI
PDF下载: 下载PDF文件 查看货源
内容描述: VT / TU映射器和M13多路复用器 [VT/TU MAPPER AND M13 MULTIPLEXER]
分类和应用: 复用器
文件页数/大小: 244 页 / 1139 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM5365 TEMAP  
DATASHEET  
PMC-1991148  
ISSUE 3  
HIGH DENSITY VT/TU MAPPER  
AND M13 MULTIPLEXER  
5
6
7
8
9
Unused  
Unused  
Unused  
Unused  
Unused  
I
I
I
I
I
-
-
-
-
-
I
I
I
I
I
-
-
-
-
-
I
I
I
I
I
-
-
-
-
-
The P1P0S1S2S3S4IR octet carries one bit of the clear channel T1 stream in the I  
bit. The R, P and S bits are unused.  
T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary  
link rate adjustments are optionally passed across the SBI via the V4. T1  
tributary alarm conditions are optionally passed across the SBI bus via the link  
rate octet in the V4 location.  
E1 Tributary Mapping  
Table 24 shows the format for mapping 63 clear channel E1s within the SPE  
octets. The I bits carry the clear channel E1 bits. The V1, V2 and V4 octets are  
not used to carry E1 data and are either reserved or used for control information  
across the interface. When enabled, the V4 octet carries clock phase information  
across the SBI. The V1 and V2 octets are unused and should be ignored by  
devices listening to the SBI bus. The V5 and R octets do not carry any  
information and are fixed to a zero value. The V3 octet carries an E1 data octet  
but only during rate adjustments as indicated by the V5 indicator signals, SDV5  
and SAV5, and payload signals, SDPL and SAPL.  
The V1, V2, V3 and V4 octets are fixed to the locations shown. All the other  
octets, shown shaded for E1#1,1, float within the allocated columns maintaining  
the same order and moving a maximum of one octet per 2KHz multi-frame. The  
position of the floating E1 is identified via the V5 Indicator signals, SDV5 and  
SAV5, which locate the V5 octet. When the E1 tributary rate is faster than the E1  
tributary nominal rate, the E1 tributary is shifted ahead by one octet which is  
compensated by sending an extra octet in the V3 location. When the E1  
tributary rate is slower than the nominal rate the E1 tributary is shifted by one  
octet which is compensated by inserting a stuff octet in the octet immediately  
following the V3 octet and delaying the octet that was originally in that position.  
Table 24  
– E1 Framing Format  
COL # E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21  
ROW # 1-18  
19  
V1  
I
20-81  
82  
V5  
I
83-144  
145  
PP  
I
146-207  
208  
209-270  
1
2
Unused  
Unused  
V1  
-
-
-
-
-
I
I
-
-
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use  
169  
 
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