STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Sꢀ Provides two independent de-jittered T1 or E1 recovered clocks for system
timing and redundancy.
Sꢀ Provides an on-board programmable binary sequence generator and detector
for error testing at DS3 rates. Includes support for patterns recommended in
ITU-T O.151.
Sꢀ Also provides PRBS generators and detectors on each tributary for error
testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and
O.152.
Sꢀ Supports the M23 and C-bit parity DS3 formats.
Sꢀ Standalone unchannelized DS3 framer mode for access to the entire DS3
payload.
Sꢀ When configured to operate as a DS3 Framer, gapped transmit and receive
clocks can be optionally generated for interface to link layer devices which
only need access to payload data bits.
Sꢀ DS3 Transmit clock source can be selected from either an external oscillator
or from the receive side clock (loop-timed).
Sꢀ Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU-
11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3
mapper.
Sꢀ Register level compatibility with the PM8315 TEMUX, the PM4388 TOCTL
Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET
E1/T1 transceiver and the PM8313 D3MX M13 Multiplexer/Demultiplexer.
Sꢀ Provides a generic 8-bit microprocessor bus interface for configuration,
control and status monitoring.
Sꢀ Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
Sꢀ Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant.
Sꢀ 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial
temperature range (-40oC to 85oC) operation.
Each one of 28 T1 performance monitoring sections:
Sꢀ Frames to DS-1 signals in SF and ESF formats.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
2
PMC [ PMC-SIERRA, INC ]
