STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
FIGURE 65: XCLK INPUT TIMING .................................................................222
FIGURE 66: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : CLEAR
CHANNEL MODE............................................................................................223
FIGURE 67: EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE............................................................................................224
FIGURE 68: INGRESS INTERFACE TIMING - CLOCK MASTER MODES....225
FIGURE 69: TRANSMIT LINE INTERFACE TIMING ......................................226
FIGURE 70: REMOTE SERIAL ALARM PORT TIMING..................................228
FIGURE 71: JTAG PORT INTERFACE TIMING..............................................230
FIGURE 72: 324 PIN PBGA 23X23MM BODY................................................232
TABLES
TABLE 1 - E1-FRMR FRAMING STATES......................................................62
TABLE 2 - PATH SIGNAL LABEL MISMATCH STATE ..................................85
TABLE 3 - ASYNCHRONOUS T1 TRIBUTARY MAPPING............................86
TABLE 4 - ASYNCHRONOUS E1 TRIBUTARY MAPPING ...........................87
TABLE 5 - DESYNCHRONIZER CLOCK GENERATION ALGORITHM........89
TABLE 6 - ASYNCHRONOUS DS3 MAPPING TO STS-1 (STM-0/AU3).......90
TABLE 7 - DS3 AIS FORMAT. .......................................................................90
TABLE 8 - DS3 DESYNCHRONIZER CLOCK GAPPING ALGORITHM. ......92
TABLE 9 - DS3 SYNCHRONIZER BIT STUFFING ALGORITHM. ................97
TABLE 10 - REGISTER MEMORY MAP .......................................................102
TABLE 11 - INSTRUCTION REGISTER........................................................136
TABLE 12 - IDENTIFICATION REGISTER....................................................137
TABLE 13 - BOUNDARY SCAN CHAIN ........................................................137
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