PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Figure 24
- STM-1 Output Bus Timing - AU4 VC Case
SCLK
OTMF[n]
(OTMFH4=0)
••••
OTV5[n]
OTPL[n]
TPOH[n]
OC1J1V1[n]
OPL[n]
A2 C1
X
X
J1
R
R
R
R
R
R
V1
H4
R
R
R
R
R
R
V5
Z6
OD[7:0] (n=1)
OD[15:8] (n=2)
OD[23:16] (n=3)
OD[31:24] (n=4)
National
bytes
Implicit location
of VC4 J1 byte
Last H4 byte
in tributary
multiframe
Fixed
Stuff
Columns
V5 byte TU #1,
TUG2 #1, TUG3 #1
First R column of TUG3 #1
V1 byte TU #1, TUG2 #1, TUG3 #1
Z6 byte TU #1,
TUG2 #1, TUG3 #3
Figure 25 shows a simple four STS-3 case that outlines the function of the
various output signals associated with the OD[7:0] output bus when the
TUPP+622 is in STM-4 (STS-12) output interface mode (OHSMODEB set low).
Data on OD[7:0] is updated on the rising edge of HSCLK. The OC1J1V1[1]
signal pulses high with OPL[1] signal set low to mark the position of the C1 byte
of the first STS-1 stream in every frame of the STS-12 transport envelope on
OD[7:0]. In STS-1 mode, the position of the J1 bytes and the STS-1 SPEs in an
STS-3 is determined by the value written to the corresponding STP Outgoing
Pointer MSB and LSB registers. All three STS-1 SPEs are aligned in an STS-3
stream. This register settable alignment is reflected in the outgoing control
signals OC1J1V1[1] and OPL[1]. OC1J1V1[1] pulses high with OPL[1] set high to
mark the J1 bytes and the third byte after J1 of the first tributary in each STS-1
stream within the STS-12. OPL[1] identifies the SPE bytes on OD[7:0]. The
OTMF[1] input marks the frame containing V1 bytes. It is sampled only at the first
V1 byte position of the first STS-1 stream in each of the STS-3 #1, #2, #3 and #4
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
398
PMC [ PMC-SIERRA, INC ]
