PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
The three tributary payload processors (VTPP) in an STM-1 (STS-3) tributary
processor (STP) may be individually disabled or bypassed using the
corresponding TUGEN or TUGBYP register bits, respectively. Incoming data
destined to a disabled or bypassed processor is re-transmitted unchanged to the
outgoing data after some delay. The amount of delay from the incoming to the
outgoing data stream is a function of the internal data-path pipeline delay. Figure
26 shows the delay for the end to end data path delay from ID[7:0] input to
OD[7:0] output in the STM-1 (STS-3) interface mode (IHSMODEB and
OHSMODEB set high). The delay from the rising edge of SCLK where
TUPP+622 samples ID[7:0] to the rising edge of SCLK where a downstream
device samples OD[7:0] is 7 cycles. This diagram also applies to the ID[15:8],
ID[23:16] and ID[31:24] input buses and their corresponding output buses. This
end-to-end data-path delay is also applicable to the transport frame delay
between IC1J1[1] (IC1J1[2], IC1J1[3], IC1J1[4]) and the OC1 portion of
OC1J1V1[1] (OC1J1V1[2], OC1J1V1[3], OC1J1V1[4]) in normal tributary
processing mode.
Figure 26
- STM-1 (STS-3) Interface, By-passed and Normal Transport
Frame Delay Functional Timing
SCLK
C1
IC1J1[1]
OC1J1V1[1]
C1
A2 C1 C1 C1
ID[7:0]
A1 A1 A1 A2 A2 A2 C1 C1 C1
OD[7:0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
400
PMC [ PMC-SIERRA, INC ]
