PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
The three tributary payload processors (VTPP) in each of the four STM-1 (STS-3)
tributary processors (STP) in the TUPP+622 may be individually disabled or
bypassed using the corresponding TUGEN or TUGBYP register bits, respectively.
Incoming data destined to a disabled or bypassed processor is re-transmitted
unchanged to the outgoing data after some delay. The amount of delay from the
incoming to the outgoing data stream is a function of the internal data-path
pipeline delay and the relative phase of the corresponding incoming frame pulse
(IC1J1[1]) and the GSCLK_FP input signal. Figure 27 shows the end to end data
path delay from ID[7:0] input to OD[7:0] output for the four possible alignments of
IC1J1[1] in relation to GSCLK_FP when TUPP+622 is in the STM-4 (STS-12)
interface mode (IHSMODEB and OHSMODEB set low). The delay from the rising
edge of HSCLK where TUPP+622 samples ID[7:0] to the rising edge of HSCLK
where a downstream device samples OD[7:0] is 30, 31, 32 or 33 cycles for an
IC1/GSCLK_FP offset of zero, one, two or three respectively. This end-to-end
data-path delay is also applicable to the transport frame delay between IC1J1[1]
and the OC1 portion of OC1J1V1[1] in normal tributary processing mode.
Figure 27
- STM-4 (STS-12) Interface, By-passed and Normal Transport
Frame Delay Functional Timing
HSCLK
C1
IC1J1[1]
IC1/GSCLK_FP
OFFSET BY 3 CLK.
0
1
2
3
GSCLK_FP
OC1J1V1[1]
C1
A2 C1 C1 C1
C1 C1 C1 C1 C1 C1 C1
ID[7:0]
A2 A2 A2 A2 A2 A2 A2 A2 C1 C1 C1 C1
OD[7:0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
401
PMC [ PMC-SIERRA, INC ]
