PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Shift-IR:
The shift instruction register state is used to shift both the instruction register and
the selected test data registers by one stage. Shifting is from MSB to LSB and
occurs on the rising edge of TCK.
Update-IR:
The update instruction register state is used to load a new instruction into the
instruction register. The new instruction must be scanned in using the Shift-IR
state. The load occurs on the falling edge of TCK.
The Pause-DR and Pause-IR states are provided to allow shifting through the
test data and/or instruction registers to be momentarily paused.
The TDO output is enabled during states Shift-DR and Shift-IR. Otherwise, it is
tri-stated.
13.7.2 Boundary Scan Instructions
The following is a description of the standard instructions. Each instruction
selects an serial test data register path between input, TDI, and output, TDO.
BYPASS
The bypass instruction shifts data from input TDI to output TDO with one TCK
clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other
devices. When the current instruction is the EXTEST instruction, the boundary
scan register is place between input TDI and output TDO. Primary device inputs
can be sampled by loading the boundary scan register using the Capture-DR
state. The sampled values can then be viewed by shifting the boundary scan
register using the Shift-DR state. Primary device outputs can be controlled by
loading patterns shifted in through input TDI into the boundary scan register
using the Update-DR state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
387
PMC [ PMC-SIERRA, INC ]
