PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 2000H: Master Test
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
PMCTST
MOTOTST
IOTST
X
X
X
X
X
0
W
W
R/W
W
HIZDATA
HIZIO
X
0
R/W
This register is used to enable TUPP+622 test features. All bits, except PMCTST,
are reset to zero by a reset of the TUPP+622.
HIZIO,HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the TUPP+622 .
While the HIZIO bit is a logic 1, all output pins of the TUPP+622 except the
data bus are held in a high-impedance state. The microprocessor interface is
still active. While the HIZDATA bit is a logic 1, the data bus is also held in a
high-impedance state which inhibits microprocessor read cycles.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the test
registers and control the test mode in each TSB block in the TUPP+622 for
board level testing. When IOTST is a logic 1, all blocks are held in test mode
and the microprocessor may write to a block's test mode 0 registers to
manipulate the outputs of the block and consequently the device outputs
(refer to the "Test Mode 0 Details" in the "Test Features" section).
MOTOTST:
The MOTOTST bit is used to test the decoding of the RDB_E and WRB_RWB
control signals when MBEB is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
329
PMC [ PMC-SIERRA, INC ]
