PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 2001H: STP Select
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
W
W
W
STPSEL[1]
STPSEL[0]
SSEL[1]
SSEL[0]
Unused
Unused
Unused
Unused
X
X
X
X
X
X
X
X
This register is used to select the STM-1 (STS-3) Tributary Processor (STP) and
the VTPP, RTOP, RTTB slice when the PMC's manufacturing test mode for the
TUPP+622 is enabled.
SSEL[1:0]:
The test mode (TSB) slice selection bits (SSEL[1:0]) control CBI access to the
VTPP[3:1], RTOP[3:1] and RTTB[3:1] of a selected STP when PMCTST is set
high. When SSEL is set to 'b00, the selection among the TSBs in STP #1 - #4
is directly controlled by the address bus (A[13:0]). When SSEL is set to the
three higher values, TSB selection is a combination of the address bus, the
STPSEL values and the SSEL values. The STP is selected by the STPSEL
values. The selection among the VTPP, RTOP and RTTB TSBs is made by
setting the address to the address range of VTPP #1, RTOP #1 and RTTB #1,
respectively. The choice of TSB slice #1, #2 and #3 is controlled by writing
'b01, 'b10 and 'b11, respectively, to the SSEL[1:0] bits. The SSEL[1:0] bits are
cleared by setting CSB to logic 1.
STPSEL[1:0]:
The test mode STP selection bits (STPSEL[1:0]) control CBI access to the
STP #1, #2, #3 and #4 when PMCTST is set high and the SSEL[1:0] bits are
set to ‘b01, ‘b10 or ‘b11. The choice of STP #1, #2, #3 or #4 is controlled by
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
331
PMC [ PMC-SIERRA, INC ]
