PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
STP #1
STP #2
STP #3
STP #4
3C01H
3C02H
3C03H
Register
RTTB #1 Test Register 1
RTTB #1 Test Register 2
RTTB #1 Test Register 3
Reserved
2401H
2402H
2403H
2404H-
243FH
2C01H
2C02H
2C03H
2C04H-
2C3FH
3401H
3402H
3403H
3404H-
343FH
3C04H-
3C3FH
2440H -
2443H
2444H-
247FH
2C40H -
2C43H
2C44H-
2C7FH
3440H -
3443H
3444H-
347FH
3C40H -
3C43H
3C44H-
3C7FH
RTTB #2 Test Register 0 - 3
Reserved
2480H -
2483H
2484H-
27FFH
2C80H -
2C83H
2C84H-
2FFFH
3480H -
3483H
3484H-
37FFH
3C80H -
3C83H
3C84H-
3FFFH
RTTB #3 Test Register 0 - 3
Reserved
Notes on Test Mode Register Bits:
1.
Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic 0. Reading back unused bits
can produce either a logic 1 or a logic 0; hence unused register bits should be
masked off by software when read.
2.
Writeable test mode register bits are not initialized upon reset unless
otherwise noted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
328
PMC [ PMC-SIERRA, INC ]
