PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
12
TEST FEATURES DESCRIPTION
Simultaneously asserting (low) the CSB, RDB and WRB inputs when the MBEB
input is negated (high), causes all output pins and the data bus to be held in a
high-impedance state. This test feature may be used for board testing.
Test mode registers are used to apply test vectors during production testing of
the TUPP+622. Test mode registers (as opposed to normal mode registers) are
selected when A[13] is high.
Test mode registers may also be used for board testing. When all of the tributary
payload processors within the TUPP+622 are placed in test mode 0, device
inputs may be read and device outputs may be forced via the microprocessor
interface (refer to the section "Test Mode 0" for details).
Table 3
STP #1
- Test Mode Register Memory Map
STP #2
STP #3
STP #4
Register
0000H-
07FFH
0800H-
0FFFH
1000H-
17FFH
1800H-
1FFFH
Normal Mode Registers
2000H
2001H
2002H
2003H
2004H
2005H
2006H
Master Test Register
STP Select Register
I/O Test register 1
I/O Test register 2
I/O Test register 3
I/O Test register 4
I/O Test register 5
Reserved
2802H
2803H
2804H
2805H
2806H
3002H
3003H
3004H
3005H
3006H
3802H
3803H
3804H
3805H
3806H
2006H-
201FH
2806H-
281FH
3006H-
301FH
3806H-
381FH
2020H
2021H
2022H
2820H
2821H
2822H
3020H
3021H
3022H
3820H
3821H
3822H
VTPP #1 Test Register 0
VTPP #1 Test Register 2
VTPP #1 Test Register 4
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
325
PMC [ PMC-SIERRA, INC ]
