PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 104H, 204H, 304H: RTOP, TU3 or TU #1 in TUG2 #1, BIP-2/BIP-8
Error Count LSB
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
BIP[7]
BIP[6]
BIP[5]
BIP[4]
BIP[3]
BIP[2]
BIP[1]
BIP[0]
X
X
X
X
X
X
X
X
Register 105H, 205H, 305H: RTOP, TU3 or TU #1 in TUG2 #1, BIP-2/BIP-8
Error Count MSB
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
BIP[15]
BIP[14]
BIP[13]
BIP[12]
BIP[11]
BIP[10]
BIP[9]
X
X
X
X
X
X
X
X
BIP[8]
In TU3 mode (TU3 bit in VTPP Configuration register set high), these registers
report the number of block interleave parity (BIP-8) errors detected in the TU3
mapped into a TUG3 handled by the RTOP. Out of TU3 mode, this register
reports the number of block interleave parity (BIP-2) errors detected in TU #1 in
TUG2 #1. These registers do not saturate.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
213
PMC [ PMC-SIERRA, INC ]
