PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
BIP[15:0]:
The BIP[15:0] bits report the number of tributary path bit-interleaved parity
errors that have been detected since the last time the BIP-2/BIP-8 registers
were polled. The BIP-2/BIP-8 registers are polled by writing to the Input
Signal Activity, Accumulate Trigger register. The write access transfers the
internally accumulated error count to the BIP-2/BIP-8 registers within 10 µs
and simultaneously resets the internal counter to begin a new cycle of error
accumulation. BIP-2/BIP-8 errors may be accumulated on a nibble/bit basis or
block basis as controlled by the BLKBIP register bit. In TU3 mode, all
BIP[15:0] are valid. Out of TU3 mode, only BIP[10:0] are valid, BIP[15:11] are
held low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
214
PMC [ PMC-SIERRA, INC ]
