PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 03H: STP Reset and Identity
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
R
R
R
R
R
R
RESET
TYPE
ID[5]
ID[4]
ID[3]
ID[2]
ID[1]
ID[0]
0
1
0
0
0
0
0
1
This register allows the revision of the TUPP+622 to be read by software
permitting graceful migration to support for newer, feature enhanced versions of
the TUPP+622, should revision of the TUPP+622 occur. It also provides software
reset capability.
ID[5:0]:
The ID bits can be read to provide a binary TUPP+622 revision number.
TYPE:
This legacy TYPE bit is set high in the TUPP+622 to indicate the TUPP-PLUS
(like) functionality provided by each STP. This bit is implemented in the
TUPP+622 to maintain software backward compatibility with the TUPP-PLUS
(PM5362) device.
RESET:
The RESET bit allows the associated STP in the TUPP+622 to be reset under
software control. If the RESET bit is a logic 1, the STP is held in reset. This bit
is not self-clearing. Therefore, a logic 0 must be written to bring the STP out
of reset. Holding the STP in a reset state places it into a low power, stand-by
mode. A hardware reset clears the RESET bit, thus negating the software
reset. Otherwise the effect of a software reset is equivalent to that of a
hardware reset for the STP.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
124
PMC [ PMC-SIERRA, INC ]
