PM5362TUPP-PLUS
DATA SHEET
PMC-951010
ISSUE 6
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR
Register 02H: Input Signal Activity Monitor, AccumulationTrigger
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
OTMFA
OPLA
OC1J1A
IDA
X
X
X
X
X
X
X
X
ITMFA
IPLA
IC1J1A
SCLKA
This register provides activity monitoring on major TUPP-PLUS inputs. When a
monitored input makes a low to high transition, the corresponding register bit is
set high. The bit will remain high until this register is read, at which point, all the
bits in this register are cleared. A lack of transitions is indicated by the
corresponding register bit reading low. This register should be read periodically
to detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the RTOP
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
cleared to begin accumulating events for a new accumulation interval. To prevent
loss of data, accumulation intervals must be 0.5 second or shorter. The bits in
this register are not affected by write accesses.
SCLKA:
The SCLK active (SCLKA) bit monitors for low to high transitions on the SCLK
input. SCLKA is set high on a rising edge of SCLK, and is set low when this
register is read.
IC1J1A:
The IC1J1 active (IC1J1A) bit monitors for low to high transitions on the IC1J1
input. IC1J1A is set high on a rising edge of IC1J1, and is set low when this
register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
72
PMC [ PMC-SIERRA, INC ]
