PM5362TUPP-PLUS
DATA SHEET
PMC-951010
ISSUE 6
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR
Register 03H: Master Reset and Identity
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
RESET
TYPE
ID[5]
0
1
0
0
0
0
0
1
R
R
ID[4]
R
ID[3]
R
ID[2]
R
ID[1]
R
ID[0]
This register allows the revision of the TUPP-PLUS to be read by software
permitting graceful migration to support for newer, feature enhanced versions of
the TUPP-PLUS, should revision of the TUPP-PLUS occur. It also provides
software reset capability.
ID[5:0]:
The ID bits can be read to provide a binary TUPP-PLUS revision number.
TYPE:
The TYPE bit can be read to distinguish between the TUPP-PLUS and the
TUPP devices. The TYPE bit is set high in the TUPP-PLUS and set low in the
TUPP device.
RESET:
The RESET bit allows the TUPP-PLUS to be reset under software control. If
the RESET bit is a logic 1, the entire TUPP-PLUS is held in reset. This bit is
not self-clearing. Therefore, a logic 0 must be written to bring the
TUPP-PLUS out of reset. Holding the TUPP-PLUS in a reset state places it
into a low power, stand-by mode. A hardware reset clears the RESET bit,
thus negating the software reset. Otherwise the effect of a software reset is
equivalent to that of a hardware reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
