PM5362TUPP-PLUS
DATA SHEET
PMC-951010
ISSUE 6
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR
IOP:
The IOP bit controls the expected parity on the incoming parity signal IDP.
When IOP is set high, the parity of the parity signal set, together with IDP is
expected to be odd. When IOP is set low, the expected parity is even.
Membership of the parity signal set always includes ID[7:0], and may include
input signals IC1J1 and IPL as controlled by the INCIC1J1 and INCIPL bits,
respectively.
INCIC1J1:
The INCIC1J1 bit controls whether the IC1J1 input signal participates in the
incoming parity calculations. When INCIC1J1 is set high, the parity signal set
includes the IC1J1 input. When INCIC1J1 is set low, parity is calculated
without regard to the state of IC1J1. Selection of odd or even parity is
controlled by the IOP bit.
INCIPL:
The INCIPL bit controls the whether the IPL input signal participates in the
incoming parity calculations. When INCIPL is set high, the parity signal set
includes the IPL input. When INCIPL is set low, parity is calculated without
regard to the state of IPL. Selection of odd or even parity is controlled by the
IOP bit.
LOPAIS:
The LOPAIS bit is an active high AIS insertion enable. When LOPAIS is set
high, AIS is automatically generated on the outgoing data stream for all
tributaries that are in loss of pointer state. When LOPAIS is set low, the
generation of AIS on the outgoing data stream is inhibited. This bit is logically
OR'ed with the bit of the same name in Tributary Alarm AIS Control register.
IPE:
The IPE bit is an active high interrupt enable. When IPE is set high, the
occurrence of a parity error on the incoming parity signal set will cause an
interrupt to be asserted on the interrupt (INTB) output. When IPE is set low,
incoming parity errors will not cause an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
68
PMC [ PMC-SIERRA, INC ]
