PM5362TUPP-PLUS
DATA SHEET
PMC-951010
ISSUE 6
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR
7
PIN DESCRIPTION
Pin Name Type
Pin
Function
No.
SCLK/
Input
153
The system clock (SCLK) provides timing for
TUPP-PLUS internal operations. SCLK is a
19.44 MHz, nominally 50% duty cycle, clock.
When either incoming interface is in nibble mode
(IBMODE set low) or the outgoing interface is in
nibble mode (OBMODE set low), SCLK must be
connected to GSCLK[0] externally.
In incoming byte interface mode (IBMODE set
high), IC1J1, IPL, ITMF, IDP, ID[7:0], OTMF,
OC1J1 and OPL are sampled on the rising edge
of SCLK. In outgoing byte interface mode
(OBMODE set high), ODP, OTPL, OTV5,
OD[7:0], AIS, IDLE, TPOH, LC1J1V1, LPL, and
LOM[3:1] are updated on the rising edge of
SCLK.
VCLK
The test vector clock (VCLK) signal is used
during TUPP-PLUS production testing to verify
manufacture.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
PMC [ PMC-SIERRA, INC ]
