PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
supply voltage drops below the minimum operating level. See the CSPI-622 register description
for more information.
Parallel to Serial Converter
The Parallel to Serial Converter (PISO) converts the transmit byte serial stream to a bit serial
stream. The transmit bit serial stream appears on the TXD+/- PECL output. When the parallel
transmit interface mode is used, the PISO block is not used.
10.8 Transmit Section Overhead Processor (TSOP)
The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2),
scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion.
Line AIS Insert
Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 before scrambling
except for the section overhead. The Line AIS Insert Block substitutes all ones as described
when enabled by the TLAIS input or through an internal register accessed through the
microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to frame
boundaries.
BIP-8 Insert
The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the transmit
stream.
The BIP-8 calculation is based on the scrambled data of the complete STS-12c/STM-4-4c frame.
The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details
are provided in the references. The calculated BIP-8 code is then inserted into the B1 byte of the
following frame before scrambling. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.
Framing and Identity Insert
The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and trace/growth bytes
(J0/Z0) into the STS-12c/STM-4-4c frame. Framing bit errors may be continuously inserted under
register control for diagnostic purposes.
Scrambler
The Scrambler Block utilizes a frame synchronous scrambler to process the transmit stream
when enabled through an internal register accessed via the microprocessor interface. The
7
6
generating polynomial is x + x + 1. Precise details of the scrambling operation are provided in
the references. Note that the framing bytes and the identity bytes are not scrambled. All zeros
may be continuously inserted (after scrambling) under register control for diagnostic purposes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
54
PMC [ PMC-SIERRA, INC ]
