PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Performance Monitor
The Performance Monitor consists of two 12-bit saturating HCS error event counters and a 21-bit
saturating receive cell counter. The first error counter accumulates correctable HCS errors, which
are HCS single-bit errors, detected and corrected while the HCS Verification state machine is in
the ’Correction Mode’ state. The second error counter accumulates uncorrectable HCS errors,
which are HCS bit errors detected while the HCS Verification state machine is in the ’Detection
Mode’ state or HCS bit errors detected but not corrected while the state machine is in the
’Correction Mode’ state. The 21-bit receive cell counter counts all cells written into the receive
FIFO. Filtered cells are not counted.
Each counter may be read through the microprocessor interface. Circuitry is provided to latch
these counters so that their values can be read while simultaneously resetting the internal
counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of
any events. It is intended that the counter be polled at least once per second so as not to miss
any counted events.
Receive FIFO
The Receive FIFO block contains storage for 4 cells, along with management circuitry for reading
and writing the FIFO. The receive FIFO provides for the separation of the physical layer timing
from the system timing.
Receive FIFO management functions include filling the receive FIFO, indicating when cells are
available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers,
and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO discards the
current cell and discards the incoming cells until there is room in the FIFO. FIFO overruns are
indicated through a maskable interrupt and register bit and are considered a system error.
10.7 Transmit Line Interface (CSPI-622)
The Transmit Line Interface allows to directly interface the S/UNI-622-MAX with optical modules
(ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel to
serial conversion on the incoming outgoing 622.08 Mbit/s data stream.
Clock Synthesis
The transmit clock is synthesized from a 77.76. MHz reference by the clock synthesis unit (CSU).
The transfer function yields a typical low pass corner of 1 MHz, above which reference jitter is
attenuated at least 20 dB per octave. The design of the loop filter and PLL is optimized for
minimum intrinsic jitter. With a jitter free 77.76 MHz reference, the intrinsic jitter is typically less
than 0.07 UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency.
The REFCLK reference should be within ±20 ppm to meet the SONET/SDH free-run accuracy
requirements specified in GR-253-CORE. The CSU may require a software reset when the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
53
PMC [ PMC-SIERRA, INC ]
