PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
UTOPIA Level 2 Interface
The UTOPIA Level 2 compliant interface accepts a read clock (RFCLK) and read enable signal
(RENB). The interface indicates the start of a cell (RSOC) and the receive cell available status
(RCA) when data is read from the receive FIFO (using the rising edges of RFCLK). The RCA
status changes from available to unavailable when the FIFO is either empty (when RCALEVEL0
is high) or near empty (when RCALEVEL0 is low). This interface also indicates FIFO overruns
via a maskable interrupt and register bits. Read accesses while RCA is a logic zero will output
invalid data. The FIFO is reset on FIFO overrun, causing up to 4 cells to be lost.
UTOPIA Level 3 Interface
The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read enable signal
(RENB). The interface indicates the start of a cell (RSOC) when data is read from the receive
FIFO (using the rising edges of RFCLK). The RVAL signal indicates when data on the receive
data bus RDAT[7:0] is valid. The RPRTY signal reports the parity on the RDAT[7:0] bus
(selectable as odd or even parity). RVAL will not assert until RENB is asserted. This interface
also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while
RVAL is low are ignored and will output invalid data. The FIFO is reset on FIFO overrun, causing
up to 4 cells to be lost.
10.12.2 Transmit ATM Interface
The ATM Transmit FIFO (TXCP) provides FIFO management and the S/UNI-622-MAX transmit
cell interface. The transmit FIFO contains four cells. The FIFO depth may be programmed to
four, three, two, or one cells. The FIFO provides the cell rate decoupling function between the
transmission system physical layer and the ATM layer.
In general, the management functions include emptying cells from the transmit FIFO, indicating
when the transmit FIFO is full, maintaining the transmit FIFO read and write pointers and
detecting a FIFO overrun condition.
The interface can be configured either as a 16-bit UTOPIA Level 2 interface, or as an 8-bit
UTOPIA Level 3 interface.
UTOPIA Level 2 Interface
The UTOPIA Level 2 compliant interface accepts a write clock (TFCLK), a write enable signal
(TENB), the start of a cell (TSOC) indication, and the parity bit (TPRTY), when data is written to
the transmit FIFO (using the rising edges of TFCLK). The interface provides the transmit cell
available status (TCA) which can transition from "available" to "unavailable" when the transmit
FIFO is near full (when TCALEVEL0 is low) or when the FIFO is full (when TCALEVEL0 is high)
and can accept no more writes. To reduce FIFO latency, the FIFO depth at which TCA indicates
"full" can be set to one, two, three or four cells by the FIFODP[1:0] bits of the TXCP Configuration
2 register. If the programmed depth is less than four, more than one cell may be written after
TCA is asserted as the TXCP still allows four cells to be stored in its FIFO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
58
PMC [ PMC-SIERRA, INC ]
