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PM5356-BI 参数 Datasheet PDF下载

PM5356-BI图片预览
型号: PM5356-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM Network Interface, 1-Func, CMOS, PBGA304, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 278 页 / 1562 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC-Sierra, Inc.  
PM5356  
S/UNI-622-MAX  
DATASHEET  
S/UNI-622-MAX  
PMC-1980589  
ISSUE 5  
SATURN USER NETWORK INTERFACE (622-MAX)  
9
PIN DESCRIPTION  
9.1  
Serial Line Side Interface Signals  
Pin Name  
Type  
Pin  
No.  
Function  
RBYP  
Input  
E21  
The receive bypass (RBYP) input disables clock recovery. If  
RBYP is high, RXD+/- is sampled on the rising edge of  
RRCLK+/-. If RBYP is low, the receive clock is recovered from  
the RXD+/- bit stream.  
Please refer to the Operation section for a discussion of the  
operating modes.  
PECLV  
Input  
D22  
The PECL signal voltage select (PELCV) selects between 3.3V  
PECL signaling and 5V PECL signaling for the PECL inputs.  
When PECLV is low, the PECL inputs expect a 5V PECL signal.  
When PECLV is high, the PECL inputs expect a 3.3V PECL  
signal. The PECL biasing pins PBIAS should be set to the  
appropriate voltage to prevent latchup.  
Please refer to the Operation section for a discussion of PECL  
interfacing issues.  
REFCLK+  
REFCLK-  
Differential Y2  
PECL Input AA1  
The differential reference clock inputs (REFCLK+/-) provides a  
jitter-free 77.76 MHz reference clock for both the clock recovery  
and the clock synthesis circuits. REFCLK+/- is not required if  
the clock recovery and clock synthesis features are not used.  
Please refer to the Operation section for a discussion of PECL  
interfacing issues and reference clocks.  
RXD+  
RXD-  
Differential W1  
PECL Input V2  
The receive differential data PECL inputs (RXD+/-) contain the  
NRZ bit serial receive stream. The receive clock is recovered  
from the RXD+/- bit stream when RBYP is set low. RXD+/- is  
sampled on the rising edge of RRCLK+/- when RBYP is set  
high.  
Please refer to the Operation section for a discussion of PECL  
interfacing issues.  
RRCLK+  
RRCLK-  
Differential U1  
PECL Input U2  
When clock recovery is bypassed (RBYP set high), RRCLK+/- is  
nominally a 622.08 MHz 50% duty cycle clock and provides  
timing for the S/UNI-622-MAX receive functions. In this case,  
RXD+/- is sampled on the rising edge of RRCLK+/-. RRCLK+/-  
is ignored when RBYP is set low.  
Please refer to the Operation section for a discussion of PECL  
interfacing issues.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERSINTERNAL USE  
16  
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