PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
No line rate clocks are required directly by the S/UNI-622-MAX as it synthesizes the transmit
clock and recovers the receive clock using a 77.76 MHz reference clock. The S/UNI-622-MAX
outputs a differential PECL line data (TXD+/-).
The S/UNI-622-MAX is configured, controlled and monitored via a generic 8-bit microprocessor
bus interface. The S/UNI-622-MAX also provides a standard 5 signal IEEE 1149.1 JTAG test port
for boundary scan board test purposes.
The S/UNI-622-MAX is implemented in low power, +3.3 Volt, CMOS technology. It has TTL
compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and
outputs support 3.3V and 5.0V compatible pseudo-ECL (PECL). The S/UNI-622-MAX is
packaged in a 304 pin SBGA package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PMC [ PMC-SIERRA, INC ]
