PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Pin Name
Type
Pin
No.
Function
FPIN
Input
AB17
The active-high framing position input (FPIN) signal indicates
the SONET/SDH frame position on the PIN[7:0] bus. In parallel
interface operation, the byte on the PIN[7:0] bus indicated by
FPIN is the third A2 of the SONET/SDH framing pattern. FPIN is
sampled on the rising edge of PICLK.
When parallel interface operation is not used, FPIN may be used
for 1+1 APS operation. In this mode, FPIN marks the marks the
first synchronous payload envelope byte after the J0/Z0 bytes on
PIN[7:0]. See the Operation section for more discussion of 1+1
APS.
PIN[0]
PIN[1]
PIN[2]
PIN[3]
PIN[4]
PIN[5]
PIN[6]
PIN[7]
Input
AB18
AA17
AB16
AA16
Y16
AC15
AB15
AA15
In parallel interface operation, the data input (PIN[7:0]) bus
carries the byte-serial STS-12c/STM-4-4c or STS-3c/STM-1
stream. PIN[7] is the most significant bit (corresponding to bit 1
of each serial byte, the first bit received). PIN[0] is the least
significant bit (corresponding to bit 8 of each serial byte, the last
bit received). PIN[7:0] is sampled on the rising edge of PICLK.
When parallel interface operation is not used, PIN[7:0] may be
used for 1+1 APS operation. In this mode, PIN[7:0] carries the
byte-serial STS-12c/STM-4-4c transmit path. See the Operation
section for more discussion of 1+1 APS.
PTCLK
Input
Y14
The parallel transmit clock (PTCLK) provides timing for S/UNI-
622-MAX transmit function operation when the device is
configured for the parallel interface mode of operation.
When TOC3 is low, PTCLK should be a 77.76 MHz nominally
50% duty cycle clock free-running (non gapped) clock. When
TOC3 is high, PTCLK should be a 19.44 MHz nominally 50%
duty cycle clock.
FPOUT
Output
AC14
In parallel interface operation, the parallel outgoing stream frame
pulse (FPOUT) marks the frame alignment on the POUT[7:0]
bus. FPOUT marks the first synchronous payload envelope byte
after the J0/Z0 bytes. FPOUT is updated on the rising edge of
PTCLK.
When parallel interface operation is not used, FPOUT may be
used for 1+1 APS operation. In this mode, FPOUT marks the
first synchronous payload envelope byte after the J0/Z0 bytes.
FPOUT is updated on the rising edge of TCLK. See the
Operation section for more discussion of 1+1 APS.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
19
PMC [ PMC-SIERRA, INC ]
