PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
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DESCRIPTION
The PM5356 S/UNI-622-MAX SATURN User Network Interface is a monolithic integrated circuit
that implements SONET/SDH processing, ATM mapping functions at the STS-12c/STM-4-4c
622.08 Mbit/s rate.
The S/UNI-622-MAX receives SONET/SDH streams using a bit serial interface, recovers the
clock and data and processes section, line, and path overhead. The S/UNI-622-MAX can also be
configured for clock and data recovery and clock synthesis by-pass where it receives
SONET/SDH frames via a byte-serial interface. The S/UNI-622-MAX performs framing (A1, A2),
de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity
(B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line
and path remote error indications (M1, G1) are also accumulated. The S/UNI-622-MAX interprets
the received payload pointers (H1, H2) and extracts the synchronous payload envelope which
carries the received ATM cell payload.
When used to implement an ATM UNI or NNI, the S/UNI-622-MAX frames to the ATM payload
using cell delineation. HCS error correction is provided. Idle/unassigned cells may be optionally
dropped. Cells are also dropped upon detection of an uncorrectable header check sequence
error. The ATM cell payloads are descrambled and are written to a four-cell FIFO buffer. The
received cells are read from the FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz)
or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface. Counts of received
ATM cell headers that are errored and uncorrectable and those that are errored and correctable
are accumulated independently for performance monitoring purposes.
The S/UNI-622-MAX transmits SONET/SDH streams using a bit serial interface. The S/UNI-622-
MAX can also be configured for clock and data recovery and clock synthesis by-pass where it
transmits the SONET/SDH frames via a byte-serial interface. The S/UNI-622-MAX synthesizes
the transmit clock from a 77.76MHz frequency reference and performs framing pattern insertion
(A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved
parity codes (B1, B2, B3) as required to allow performance monitoring at the far end. Line and
path remote error indications (M1, G1) are also inserted. The S/UNI-622-MAX also supports the
insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit
interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester
applications.
When used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO
using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3
(clocked up to 100 MHz) datapath interface. Idle/unassigned cells are automatically inserted
when the internal FIFO contains less than one complete cell. The S/UNI-622-MAX provides
generation of the header check sequence and scrambles the payload of the ATM cells. Each of
these transmit ATM cell processing functions can be enabled or bypassed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
