欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM4351-RI 参数 Datasheet PDF下载

PM4351-RI图片预览
型号: PM4351-RI
PDF下载: 下载PDF文件 查看货源
内容描述: 联合E1 / T1收发器 [COMBINED E1/T1 TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 485 页 / 3011 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM4351-RI的Datasheet PDF文件第65页浏览型号PM4351-RI的Datasheet PDF文件第66页浏览型号PM4351-RI的Datasheet PDF文件第67页浏览型号PM4351-RI的Datasheet PDF文件第68页浏览型号PM4351-RI的Datasheet PDF文件第70页浏览型号PM4351-RI的Datasheet PDF文件第71页浏览型号PM4351-RI的Datasheet PDF文件第72页浏览型号PM4351-RI的Datasheet PDF文件第73页  
STANDARD PRODUCT  
PM4351 COMET  
DATA SHEET  
PMC-1970624  
ISSUE 10  
COMBINED E1/T1 TRANSCEIVER  
is declared and the basic frame alignment is set accordingly (i.e., the basic frame  
alignment is set to correspond to the frame alignment found by the parallel offline  
search, which is also the basic frame alignment corresponding to the newly  
found CRC multiframe alignment).  
Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for  
basic frame alignment. If, however, the 400 ms timer expires at any time during  
this procedure, the E1-FRMR stops searching for CRC multiframe alignment and  
declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be  
optionally set to either halt searching for CRC multiframe altogether, or may  
continue searching for CRC multiframe alignment using the established basic  
frame alignment. In either case, no further adjustments are made to the basic  
frame alignment, and no offline searches for basic frame alignment occur once  
CRC-to-non-CRC interworking is declared: it is assumed that the established  
basic frame alignment at this point is correct.  
AIS Detection  
When an unframed all-ones receive data stream is received, an AIS defect is  
indicated by setting the AISD bit to logic 1 when fewer than three zero bits are  
received in 512 consecutive bits or, optionally, in each of two consecutive periods  
of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512  
consecutive bits or in each of two consecutive periods of 512 bits. Finding frame  
alignment will also cause the AISD bit to be set to logic 0.  
Signaling Frame Alignment  
Once the basic frame alignment has been found, the E1-FRMR searches for  
Channel Associated Signaling (CAS) multiframe alignment using the following  
G.732 compliant algorithm: signaling multiframe alignment is declared when at  
least one non-zero time slot 16 bit is observed to precede a time slot 16  
containing the correct CAS alignment pattern, namely four zeros (“0000”) in the  
first four bit positions of timeslot 16.  
Once signaling multiframe alignment has been found, the E1-FRMR sets the  
OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors  
the signaling multiframe alignment signal, indicating errors occurring in the 4-bit  
pattern, and indicating the debounced value of the Remote Signaling Multiframe  
Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the  
Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being  
-3  
falsely indicated in the presence of a 10 bit error rate.  
The block declares loss of CAS multiframe alignment if two consecutive CAS  
multiframe alignment signals have been received in error, or additionally, if all the  
bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of  
PROPRIETARY AND CONFIDENTIAL  
45  
 复制成功!