STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
9.5
T1 Inband Loopback Code Detector (IBCD)
The T1 Inband Loopback Code Detection function is provided by the IBCD block.
This block detects the presence of either of two programmable INBAND
LOOPBACK ACTIVATE and DEACTIVATE code sequences in either framed or
unframed data streams. Each INBAND LOOPBACK code sequence is defined
as the repetition of the programmed code in the PCM stream for at least 5.1
seconds. The code sequence detection and timing is compatible with the
specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303.
LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through
internal register bits. An interrupt is generated to indicate when either code status
has changed.
9.6
T1 Pulse Density Violation Detector (PDVD)
The Pulse Density Violation Detection function is provided by the PDVD block.
The block detects pulse density violations of the requirement that there be N
ones in each and every time window of 8(N+1) data bits (where N can equal 1
through 23). The PDVD also detects periods of 16 consecutive zeros in the
incoming data. Pulse density violation detection is provided through an internal
register bit. An interrupt is generated to signal a 16 consecutive zero event,
and/or a change of state on the pulse density violation indication.
The PDVD block is available when the analog RXTIP and RXRING inputs are
enabled (i.e., when the RUNI bit in the Receive Line Interface Configuration
register is logic 0).
9.7
Performance Monitor Counters (PMON)
The Performance Monitor Counters function is provided by the PMON block.
The block accumulates CRC error events, Frame Synchronization bit error
events, Line Code Violation events, and Out Of Frame events, or optionally,
Change of Frame Alignment (COFA) events with saturating counters over
consecutive intervals as defined by the period of the supplied transfer clock
signal (typically 1 second). When the transfer clock signal is applied, the PMON
transfers the counter values into holding registers and resets the counters to
begin accumulating events for the interval. The counters are reset in such a
manner that error events occurring during the reset are not missed. If the
holding registers are not read between successive transfer clocks, an OVERRUN
register bit is asserted.
For T1, a line code violation is either a bipolar violation (only those not part of a
zero substitution code for B8ZS-coded and HDB3 signals) or excessive zeros.
Excessive zeros is a sequence of zeros greater than 15 bits long for an AMI-code
PROPRIETARY AND CONFIDENTIAL
47
PMC [ PMC-SIERRA, INC ]
