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PM4351-NI 参数 Datasheet PDF下载

PM4351-NI图片预览
型号: PM4351-NI
PDF下载: 下载PDF文件 查看货源
内容描述: 联合E1 / T1收发器 [COMBINED E1/T1 TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 485 页 / 3011 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4351 COMET  
DATA SHEET  
PMC-1970624  
ISSUE 10  
COMBINED E1/T1 TRANSCEIVER  
Register 017H: RJAT Configuration  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
CENT  
X
X
X
0
0
0
0
1
R/W  
R/W  
R/W  
R/W  
R/W  
UNDE  
OVRE  
FIFORST  
LIMIT  
CENT:  
The CENT bit allows the FIFO to self-center its read pointer, maintaining the  
pointer at least 4 UI away from the FIFO being empty or full. When CENT is  
set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data  
bit period, and for the first 384 bit periods following an overrun or underrun  
event. If an EMPTY or FULL alarm occurs during this 384 UI period, the  
period will be extended by the number of UI that the EMPTY or FULL alarm  
persists. During the EMPTY or FULL alarm conditions, data is lost. When  
CENT is set to logic 0, the self-centering function is disabled, allowing the  
data to pass through uncorrupted during EMPTY or FULL alarm conditions.  
The recommended value of CENT is logic 1.  
UNDE:  
Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB  
output low.  
OVRE:  
Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB  
output low.  
FIFORST:  
Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by  
software. When FIFORST is logic 1, writing to the PLL Divider Control  
Registers N1 and N2 will cause both the PLL and FIFO to reset. When  
PROPRIETARY AND CONFIDENTIAL  
117  
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