STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 016H: RJAT Divider N2 Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N2[7]
N2[6]
N2[5]
N2[4]
N2[3]
N2[2]
N2[1]
N2[0]
0
0
1
0
1
1
1
1
This register contains an 8-bit binary number, N2, which is one less than the
magnitude of the output clock divisor. The output clock divisor magnitude,
(N2+1), is the ratio between the frequency of the smooth output clock, BRCLK,
and the frequency applied to the phase discriminator input.
Writing to this register will reset the PLL.
Writing to this register will reset the PLL. If the FIFORST bit of the RJAT
Configuration register is set high, a write to this register will reset both the PLL
and FIFO.
The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship N1 = N2 must always be true in order for the PLL to
operate correctly.
In order to meet jitter transfer specifications for some modes, such as basic E1
operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff
frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter
transfer specifications.
For T1 mode, the recommended values are N1 = N2 = 2FH. For E1 mode, the
recommended values are N1 = N2 = FFH.
PROPRIETARY AND CONFIDENTIAL
116
PMC [ PMC-SIERRA, INC ]
