STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 01AH: TJAT Divider N2 Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N2[7]
N2[6]
N2[5]
N2[4]
N2[3]
N2[2]
N2[1]
N2[0]
0
0
1
0
1
1
1
1
This register contains an 8-bit binary number, N2, which is one less than the
magnitude of the output clock divisor. The output clock divisor magnitude,
(N2+1), is the ratio between the frequency of the smooth output clock and the
frequency applied to the phase discriminator input.
Writing to this register will reset the PLL. If the FIFORST bit of the TJAT
Configuration register is set high, a write to this register will reset both the PLL
and FIFO.
The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship Fref/(N1+1) = Fout/(N2+1) must always be true in order
for the PLL to operate correctly.
Minimizing the values of N1 and N2 while keeping the above equation true
minimizes intrinsic jitter. However, the minimum valid value for N2 is 1FH.
In order to meet jitter transfer specifications for some modes, such as basic E1
operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff
frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter
transfer specifications.
When dealing with extremely low frequency references, such as an 8kHz
reference clock, the N1 and N2 should configured so that Fref/(N1+1) and
Fout/(N2+1) are both 8kHz results. Thus, for an 8kHz reference, N1 is 00H.
PROPRIETARY AND CONFIDENTIAL
121
PMC [ PMC-SIERRA, INC ]
