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PM4341A-QI 参数 Datasheet PDF下载

PM4341A-QI图片预览
型号: PM4341A-QI
PDF下载: 下载PDF文件 查看货源
内容描述: T1成帧器/收发器 [T1 FRAMER/TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路
文件页数/大小: 288 页 / 981 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM4341AT1XC  
DATA SHEET  
PMC-900602  
ISSUE 7  
T1 FRAMER/TRANSCEIVER  
in the PCM stream for at least 5.1 seconds.The code sequence detection and  
timing is compatible with the specifications defined in T1.403-1989, TA-TSY-  
000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code  
indication is provided through internal register bits. An interrupt is generated to  
indicate when either code status has changed.  
8.7 Pulse Density Violation Detector (PDVD)  
The Pulse Density Violation Detection function is provided by the PDVD block.  
The TSB detects pulse density violations of the requirement that there be N ones  
in each and every time window of 8(N+1) data bits (where N can equal 1 through  
23).The PDVD also detects periods of 16 consecutive zeros in the incoming  
data. Pulse density violation detection is provided through an internal register bit.  
An interrupt is generated to signal a 16 consecutive zero event, and/or a change  
of state on the pulse density violation indication.  
8.8 Performance Monitor Counters (PMON)  
The Performance Monitor Counters function is provided by the PMON block.The  
TSB accumulates CRC error events, Frame Synchronization bit error events, Line  
Code Violation events, and Loss Of Frame events, or optionally, Change of  
Frame Alignment (COFA) events with saturating counters over consecutive  
intervals as defined by the period of the supplied transfer clock signal (typically 1  
second). When the transfer clock signal is applied, the PMON transfers the  
counter values into holding registers and resets the counters to begin  
accumulating events for the interval.The counters are reset in such a manner  
that error events occurring during the reset are not missed. If the holding  
registers are not read between successive transfer clocks, an OVERRUN register  
bit is asserted.  
Generation of the transfer clock within the T1XC chip is performed by writing to  
any counter register location. The holding register addresses are contiguous to  
facilitate polling operations.  
8.9 Bit Oriented Code Detector (RBOC)  
The Bit Oriented Code detection function is provided by the RBOC block.This  
block detects the presence of 63 of the possible 64 bit oriented codes  
transmitted in the Facility Data Link channel in ESF framing format, as defined in  
th  
ANSI T1.403-1989 and in TR-TSY-000194.The 64 code (111111) is similar to  
the DL FLAG sequence and is used by the RBOC to indicate no valid code  
received.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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