PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 4CH: PMON BEE Count (LSB)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
BEE7
BEE6
BEE5
BEE4
BEE3
BEE2
BEE1
BEE0
X
X
X
X
X
X
X
X
This register contains the lower eight bits of the 9-bit Bit Error event counter. A Bit
Error event is defined as a CRC-6 error in ESF, a framing bit error in SF, an F -bit
T
error in SLC®96, and an F-bit or sync bit error (there can be up to 7 bits in error
per frame) in T1DM.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
170
PMC [ PMC-SIERRA, INC ]
