PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
registers.The data contained in the holding registers can then be subsequently
read by µP accesses into the PMON count register address space.The latching
of count data, and subsequent resetting of the counters, is synchronized to the
internal event timing so that no events are missed. NOTE: it is necessary to write
to one, and only one, count register address to latch all the count data register
values into the holding registers and to reset all the counters for each polling
cycle.
The PMON is loaded with new performance data within 3.5 recovered clock
periods of the latch performance data register write. With nominal line rates, the
PMON registers should not be polled until 2.3 µsec have elapsed from the
PMON count register write.
When the T1XC is reset, the contents of the PMON count registers are unknown
until the first latching of performance data is performed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
167
PMC [ PMC-SIERRA, INC ]
