PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 49H: PMON Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Reserved
XFER
X
X
X
X
X
0
R/W
R
0
R
OVR
0
This register contains status information indicating when counter data has been
transferred into the holding registers and indicating whether the holding registers
have been overrun.
Reserved:
This bit must be programmed to logic 0 for proper operation.
XFER:
The XFER bit indicates that a transfer of counter data has occurred. A logic 1
in this bit position indicates that a latch request, initiated by writing to one of
the counter register locations, was received and a transfer of the counter
values has occurred. A logic 0 indicates that no transfer has occurred. The
XFER bit is cleared (acknowledged) by reading this register.
OVR:
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit
position indicates that a previous transfer (indicated by XFER being logic 1)
has not been acknowledged before the next transfer clock has been issued
and that the contents of the holding registers have been overwritten. A logic 0
indicates that no overrun has occurred.The OVR bit is cleared by reading this
register.
10.1.1 Registers 4A-4FH: Latching Performance Data
All the Performance Data registers are updated as a group by writing to any of
the PMON count registers (addresses 4AH-4FH). A write to any of these
locations loads performance data located in the PMON into the internal holding
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
166
PMC [ PMC-SIERRA, INC ]
