STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
derived by the DJAT PLL using CTCLK as a
reference).
The TECT3 may be configured to ignore the CTCLK
input and utilize CECLK or one of the recovered
Ingress clocks instead, RECVCLK1 and RECVCLK2.
Receive tributary clock[x] is automatically substituted
for CTCLK if line loopback is enabled.
CECLK
Input N4
Common Egress Clock (CECLK). The common
egress clock is used to time the egress interface when
Clock Slave mode is enabled in the egress side.
CECLK may be a 1.544MHz or 2.048MHz clock with
optional gapping for adaptation from non-uniform
system clocks. When the Clock Slave: EFP Enabled
mode is active, CEFP and ED[x] are sampled on the
active edge of CECLK, and EFP[x] is updated on the
active edge of CECLK. When the Clock Slave:
External Signaling mode is active, CEFP, ESIG[x] and
ED[x] are sampled on the active edge of CECLK.
CECLK is a nominal 1.544 or 2.048 MHz clock +/-
50ppm with a 50% duty cycle.
This signal shares a pin with the H-MVIP signal
CMV8MCLK. By default this input is CECLK.
CEFP
Input M2
Common Egress Frame Pulse (CEFP). CEFP may
be used to frame align the framers to the system
backplane. If frame alignment only is required, a pulse
at least 1 CECLK cycle wide must be provided on
CEFP every 193 bit times for T1 mode or every 256 bit
times for T1 and E1 modes (T1 mode using 2.048MHz
clock). If superframe alignment is required, transmit
superframe alignment must be enabled, and a pulse at
least 1 CECLK cycle wide must be provided on CEFP
every 12 or 24 frame times for T1 mode, on the first F-
bit of the multiframe.
CEFP is sampled on the active edge of CECLK as
selected by the CEFE bit in the Master Common
Egress Serial and H-MVIP Interface Configuration
register. CEFP has no effect in the Clock Master
egress modes.
PROPRIETARY AND CONFIDENTIAL
35
PMC [ PMC-SIERRA, INC ]
