STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 79: Microprocessor Interface Read Timing
tS
AR
A[13:0]
Valid
Address
tH
AR
tS
ALR
tV
tH
L
ALR
ALE
tH
tS
LR
LR
(CSB+RDB)
INTB
tZ
INTH
tZ
tP
RD
RD
D[7:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high
so parameters tSALR, tHALR, tVL, and tSLR are not applicable.
PROPRIETARY AND CONFIDENTIAL
203
PMC [ PMC-SIERRA, INC ]
