STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 80: Microprocessor Interface Write Timing
A[9:0]
Valid Address
tS
tH
ALW
ALW
tV
L
tS
tH
LW
LW
ALE
(CSB+WRB)
D[7:0]
tS
tV
tS
tH
AW
AW
WR
tH
DW
DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB
signals.
2. In non-multiplexed address/data bus architectures, ALE should be held high
so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable.
3. Parameter tHAW is not applicable if address latching is used.
4. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
5. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
PROPRIETARY AND CONFIDENTIAL
205
PMC [ PMC-SIERRA, INC ]
