STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 33: Typical Data Frame
BIT: 8
7
6
5
4
3
2
1
FLAG
0
1
1
1
1
1
1
0
Address (high)
(low)
data bytes received
and transferred to
the FIFO Buffer
CONTROL
Frame Check
Sequence
0
1
1
1
1
1
1
0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary
and universal addresses are compared with the high order packet address to
determine a match.
Figure 34: Example Multi-Packet Operational Sequence
DATA FF F D D D D F D D D D D D D D DD A FF F F DD D D FF
INT
1
2
3
4 5
6
7
FE
LA
F
A
D
- flag sequence (01111110)
- abort sequence (01111111)
- packet data bytes
INT - active high interrupt output
FE
LA
- internal FIFO empty status
- state of the LINK ACTIVE software flag
Figure 34 shows the timing of interrupts, the state of the FIFO, and the state of
the Data Link relative the input data sequence. The cause of each interrupt and
PROPRIETARY AND CONFIDENTIAL
147
PMC [ PMC-SIERRA, INC ]
